In this project for Advanced Computer Systems Architecture, two teammates and I set set out to reproduce the Central Processing Unit (CPU) of the NES on a Virtex 4 FPGA using a ML401 eval board and replace the NES CPU on the motherboard with the FPGA. We set a stretch goal of implementing the PPU as well.
The NES processor is the Ricoh 2A03. It is based on a MOS 6502 core. Beyond the 6502 core the chip has an Audio Processing Unit (APU) capable of producing the signature 8-bit audio anyone familiar with the NES will know. It also had memory mapped registers for managing sprite RAM DMA transfers and performing I/O with the controller ports, and controlling Sprite RAM DMA transfers. The Memeory Bus connects the CPU with the onboard PPU and SRAM. This bus is also used to connect with cartridges. A block diagram, the NES motherboard, highlighting of individual components, and ML401 are shown below.
First, we implemented and verified the 6502 core. Then we implemented the Controller I/O interface, DMA controller, and internals of the APU. Because the 2A03 has a 4-bit internal DAC, we needed to interface with the on board LM4550 AC '97 Codec instead, block diagram below. This required creating an LM4550 interface to replace the 4-bit DAC from the 2A03.
Once the individual components were all simulating properly we integrated them and verified the entire design. After the design level verification, we desoldered a 2A03 chip from an NES motherboard and used fly wires to connect it to the ML401. We were in the process of debugging the CPU while integrated with the NES when the course ended.